A conventional temperature compensated ECL output driver circuit is illustrated in FIG. 1. An ECL output gate having first and second ECL output gate transistors Q4,Q3 with a first common emitter node coupling N3 is coupled between high V.sub.CC and low V.sub.EE potential power rails. The ECL output gate transistors Q4,Q3 provide alternative collector current paths through respective collector node output voltage swing resistors R2,R1 according to a data input signal at a base node input V.sub.IN of the ECL output gate transistor Q3. A first current sink Q5,R4 is coupled between the common emitter node coupling N3 of the ECL output gate transistors and low potential power rail V.sub.EE. At least one emitter follower transistor output circuit Q12 is coupled to a collector node output N1 of the ECL output gate transistor Q4 for delivering logic high V.sub.OH and logic low V.sub.OL potential level output signals at an output V.sub.OUT. A temperature compensating crossover network Q1,Q2,R3 is coupled between collector nodes N1,N2 of the respective ECL output gate transistors Q4,Q3.
Disadvantages of the conventional ECL output driver circuit of FIG. 1 occur during operation in the relatively low temperature range of, for example, -10.degree. C. or -20.degree. C. to -55.degree. C. Relevant operating currents and voltage drops in the ECL output driver circuit vary with temperature because of the negative temperature coefficient of the base emitter voltage drops V.sub.BE across the base emitter junctions of the bipolar transistors, and the positive temperature coefficient of the doped semiconductor material resistors. At very low temperatures the amplification factor .beta. of the bipolar transistors may decrease for example from 100 at room temperature to e.g. 50 at -55.degree. C. In particular, as the operating temperature of the ECL output driver circuit falls through the low temperature range, the base current I.sub.B Q12 through output emitter follower transistor Q12 during the logic high potential level signal V.sub.OH at the ECL output gate output V.sub.OUT increases.
Approaching, for example, -55.degree. C., the base current I.sub.B Q12 becomes a non-negligible factor in the voltage drop V.sub.R2 across output voltage swing resistor R2. Typically, the output base current I.sub.B Q12 may be neglected at intermediate and high temperature operating ranges relative to the large collector currents through respective bipolar transistors for a logic high potential level signal at the output node N1 and final output V.sub.OUT. By way of example, V.sub.R2 remains approximately, e.g. 0.15 v. At the low temperature operating ranges of -10.degree. C. or -20.degree. C. to -55.degree. C. required for example for military specifications, however, the voltage drop V.sub.R2 across output voltage swing resistor R2 may increase to the extent that the voltage level of the final output high signal V.sub.OH falls below the permitted specification range, of, e g., -0.870 v (V.sub.OHMAX) to -1.085 v (V.sub.OHMIN) and the preferred nominal value for V.sub.OH of -0.95 v.
According to conventional methods of maintaining specifications for the output high signal V.sub.OH in the low temperature operating range, the collector path resistor R2 which along with R1 and R4 sets the swing voltage at the output node N1, is selected to have a relatively low resistance value. This permits the output logic high signal V.sub.OH to remain within the permitted specification range even at low temperature, as the base current I.sub.B Q12 increases. The logic high potential output signal V.sub.OH at the final output V.sub.OUT is given by the equation: EQU V.sub.OH =V.sub.CC -(V.sub.R2 +V.sub.BE Q12).congruent.-0.95 v 1)
The ECL output gate current sink Q5,R4 is generally operated with a current source voltage V.sub.CS so that: EQU V.sub.CS =V.sub.R4 +V.sub.BE Q5.congruent.1.32 v 2)
and: EQU V.sub.R2 =R2/R4 V.sub.R4. 3)
Swing voltage resistors R1,R2 are generally selected to have the same resistance value and tail resistor R4 is selected to have a resistance value substantially one half that of R1,R2. If the resistance value of R1,R2 is reduced to meet military specifications, the current sink tail resistor R4 is therefore also required to have a lower resistance value with the result that there is higher current and higher power dissipation necessary for operation in the low temperature range while meeting specifications for V.sub.OH.
It is noted that the conventional temperature compensating network Q1,Q2,R3 coupled between collector nodes N1,N2 of ECL output gate transistors Q4,Q3 provides temperature compensation only in the intermediate and high temperature operating ranges. The swing voltage difference of the logic high and low levels of approximately 750 mV between N1 and N2 causes a "bleed" current to flow across the network which varies with temperature to provide temperature compensation for the output base drive current I.sub.B Q12 in the intermediate and high temperature ranges. In the low temperature range noted above, the bleed current of the conventional temperature compensating crossover network saturates at approximately -10.degree. C. to -20.degree. C. and the compensating crossover network is essentially inoperative from -10.degree. C. or -20.degree. C. to -55.degree. C. The output base drive current and the value of V.sub.OH are then dependent only on the value of R2 and the voltage drop V.sub.R2 which may be too large to keep V.sub.OH within required specifications. It is for this reason that low values are selected for R2 and R4 increasing current and power dissipation for example from 2.8 mA to 4.3 mA.